Write-once or “one-time” programmable memory cells have been used in programmable read-only memory (PROM) arrays for many years. Two types of memory cells are in use and are known as “fuse” and “anti-fuse” types.
FIG. 1 of the accompanying drawings illustrates a known type of memory cell forming part of an array addressed by column electrodes such as 1 and row electrodes such as 2. Each cell comprises a fusible conductive link 3 connected in series with the source-drain channel of a transistor 4, such as N-MOS transistor. The link 3 is connected between the drain of the transistor 4 and the row electrode 2 of the row to which the cell belongs. The gate of the transistor 4 is connected to the column electrode 1 of the column to which the cell belongs. The source of the transistor 4 is connected to a common line, such as ground.
The link 3 is typically implemented in a doped poly-silicon layer. In order to program the cell, the transistor 4 is switched on and a high voltage is applied across the link 3, which causes a large current to flow through the cell. With a sufficiently high current, the link 3 is blown and becomes open circuit. Conversely, the link 3 remains intact if the transistor 4 is switched off during the application of the high programming voltage. During reading of the memory, when the cell is selected, a read-out circuit detects an open circuit if the link is blown or a closed circuit if the link is intact.
FIG. 2 of the accompanying drawings illustrates a typical architecture of an array or matrix of memory cells. The array 5 is addressed by column and row decoders 6 and 7 and is provided with read-out sense circuitry comprising or including a sense amplifier arrangement 8. A program control arrangement 9 is provided for controlling programming of the memory cells of the array 5 during a programming step.
Such a memory has several disadvantages. For example, in order to select a cell for programming, high voltages must be applied to the gate of the “selection” transistor 4. This requires the decoders to operate at supply voltages which are substantially greater than the nominal supply voltage required during memory reading operations after programming of the memory. Also, the selection transistors such as 4 must be able to pass a relatively large current during programming. This is typically achieved by making the transistors 4 sufficiently large to handle such large currents without damage. This in turn means that a relatively large area of an integrated circuit forming the memory is required and limits the number of memory cells which may be integrated in a given area of the memory device.
A memory cell of an anti-fuse type of memory is illustrated in FIG. 3 of the accompanying drawings. The memory cell comprises a selection transistor 4 whose gate is connected to a common row electrode 2 and whose drain is connected via a capacitive element 10 to a common column electrode 1.
In order to program such a memory cell, the selection transistor 4 is switched on and a high voltage is applied across the capacitive element 10. The high voltage causes breakdown of the capacitor dielectric, which is usually in the form of gate-oxide, and creates a permanent short circuit between the terminals of the capacitive element 10. Conversely, the element 10 remains intact and open-circuit if the selection transistor 4 is switched off during the application of the high programming voltage. During the read mode when the memory cell is selected, a read-out circuit detects an open circuit if the element 10 is intact or a closed circuit if the element 10 has been programmed.
Again, such a memory requires that the decoding logic operate at relatively high programming voltages in order to enable the selection transistors 4 to be switched on or off. Further, relatively thin oxides are required in the element 10 in order to minimise the programming voltages. However, such thin oxides are not always a standard process feature of the manufacturing process for making such memories. Additional processing steps may therefore be necessary and this increases the cost of manufacture of such a memory and may reduce the manufacturing yield.
Metzger L. R., “A 16 K CMOS PROM with Poly-silicon Fusible Links”, IEEE Journal of Solid State Circuits, vol. SC-18, no 5, October 1983 discloses the use of a poly-silicon fusible link in a PROM array. The memory cells of the array comprise a poly-silicon fuse connected in series with a bipolar selection transistor.
U.S. Pat. No. 5,536,968 discloses a PROM as illustrated in FIG. 4 of the accompanying drawings. In this type of memory, each memory cell comprises a selection diode connected in series with a fusible poly-silicon link. Such an arrangement again requires address and data logic which is capable of supplying relatively high programming voltages as well as sinking relatively high fusing currents.
FIG. 5 of the accompanying drawings illustrates a PROM of the type disclosed in US 2005/0174845A1. The memory is formed in poly-silicon thin film transistor (TFT) technology. Both “fuse” and “anti-fuse” elements are disclosed. Again, the decoding circuitry has to be capable of withstanding the relatively high programming voltages and the thin film transistors must be sufficiently large to be able to pass the relatively high currents required to blow the fusible elements.
FIGS. 6A and 6B of the accompanying drawings illustrate a silicided poly-silicon fuse structure formed using CMOS technology, for example as disclosed in U.S. Pat. No. 5,708,291. The structure is formed on oxide side layer 11 formed on a substrate 12 and comprises a poly-silicon layer 13 and a silicide layer 14. Contacts 15 and 16 are formed on the silicide layer 14.
The conductance of the fusible element is dominated by the low impedance of the material of the layer 14, which is a relatively low impedance silicide alloy. FIG. 6A illustrates the intact element. FIG. 6B illustrates the programmed element, in which the silicide alloy has agglomerated as shown at 17 and 18, so as to result in a relatively large increase in the impedance of the element.
Layers of silicide alloy and poly-silicon are available in many CMOS processes. However, in a typical low temperature poly-silicon TFT process, the provision of such a structure would require additional process steps.
US 2004/0156234A1 discloses a single transistor anti-fuse element formed in CMOS technology, for example as illustrated in FIG. 7 of the accompanying drawings. Each fuse element has a thicker dielectric 20 at a source end of the transistor channel as compared with the dielectric 21 at the drain end. This enables a highly doped, region to form at a predictable point in the channel when a high gate-drain voltage is applied. This in turn facilitates the formation of a short circuit between the gate and the newly formed doped region.